1. Field of the Invention
The present invention relates to an A/D-D/A converting apparatus having an A/D converting unit and a D/A converting unit, each using digital filters.
2. Description of the Prior Art
A conventional configuration of an A/D-D/A converting apparatus having both an A/D converting unit and a D/A converting unit each using digital filters is shown in a block diagram of FIG. 1.
In FIG. 1, numeral 1 designates an A/D conversion unit and numeral 2 designates an D/A conversion unit. Numeral 3 designates an input terminal of an analog input signal to the A/D conversion unit 1, numeral 4 designates an output terminal of a digital output signal from the A/D conversion unit 1, numeral 5 designates an input terminal of a digital input signal to the D/A conversion unit 2, and numeral 6 designates an output terminal of an analog output signal from the D/A conversion unit 2.
An internal configuration of A/D conversion unit 1 is as follows.
Analog input signals input at the analog input signal input terminal 3 are first input to an A/D converter 7. The A/D converter 7 is an oversampling type A/D converter which converts the analog input signal, whose sampling frequency is fs into a digital signal 8 whose oversampling frequency is a.multidot.fs (where, a=2, 3 . . . ), and outputs to a first decimation filter 9.
The first decimation filter 9 converts the digital signal 8 output from the A/D converter 7 and having the oversampling frequency a.multidot.fs into a digital signal 10 of sampling frequency b.multidot.fs (where, b&lt;a, b=1, 2 . . . ) and outputs to a second decimation filter 11, and at the same time, functions as a first digital filter (M taps) which removes folding noises generated at conversion. Numeral 17 designates a coefficient generating device which generates a coefficient for deciding characteristics of the first decimation filter 9.
The second decimation filter 11 converts the digital signal 10 output from the first decimation filter 9 having the sampling frequency b.multidot.fs into the digital signal having the sampling frequency fs, and outputs the digital signal at output terminal 4, and at the same time, functions as a second digital filter (N taps) which removes folding noises generated at conversion. Numeral 18 designates a coefficient generating device which generates a coefficient for deciding characteristics of the second decimation filter 11.
An internal configuration of the D/A conversion unit 2 is as follows.
Digital input signals input at the digital signal input terminal 5 are first input to a first interpolation filter 16. The first interpolation filter 16 converts the digital input signal whose sampling frequency is fs into a digital signal 15 whose oversampling frequency is c.multidot.fs (where, c=1, 2 . . . ), and outputs to a second interpolation filter 14, and at the same time, functions as a third digital filter (N taps) which removes image components generated at conversion. Numeral 20 designates a coefficient generating device which generates a coefficient for deciding characteristics of the first interpolation filter 16.
The second interpolation filter 14 converts the digital signal 15 outputted from the first interpolation filter 16 and having the sampling frequency c.multidot.fs into a digital signal 13 whose sampling frequency is d.multidot.fs (where, d&gt;c, d=2, 3 . . . ), and outputs the signal to the D/A converter 12, and at the same time, functions as a fourth digital filter (M taps) which removes image components generated at conversion. Numeral 19 designates a coefficient generating device which generates a coefficient for deciding characteristics of the second interpolation filter 14.
The D/A converter 12 is an oversampling type D/A converter which converts the digital signal 13 output from the second interpolation filter 14 and having the sampling frequency of d.multidot.fs into the analog signal, and outputs the analog signal to output terminal 6.
The first decimation filter 9, second decimation filter 11, first interpolation filter 16 and second interpolation filter 14, which are the first, second, third and fourth digital filters are all implemented as FIR (Finite Impulse Response) type digital filters.
Next, the operation of the conventional A/D-D/A converting apparatus thus constituted is described.
First, the operation of the A/D conversion unit 1 is described.
The analog input signal input to the A/D conversion unit 1 from the analog signal input terminal 3 is converted into the digital signal 8 of sampling frequency a.multidot.fs by the oversampling type A/D converter 7. However, the digital output signal output from the digital signal output terminal 4 must be eventually converted into the sampling frequency fs. Conversion of the sampling frequency for this purpose is a subsampling process, which is, specifically, a relatively simple process wherein digital data are only output at an interval of 1/a. However, there is a high possibility that the folding noises mix into the signal to deteriorate the accuracy of signal considerably, when it is processed simply by subsampling. Therefore, the subsampling process is performed after removing the noises by passing the digital signal through the digital filter.
The digital filter used for such a purpose should satisfy the following two conditions (a) and (b).
(a) In order to prevent folding noises, it should have a sufficient attenuation in region where there are folding noises.
(b) It should have signal passing characteristics which are as flat as possible in a signal band.
It is very difficult to realize such filter characteristics by a single stage digital filter, because a Nyquist frequency of the input signal and a frequency in the signal band are relatively separated. And hence, usually, a two-stage configuration of the first digital filter (first decimation filter 9) and the second digital filter (second decimation filter 11) is adopted as the digital filter.
The conventional A/D-D/A converting apparatus whose configuration is shown in FIG. 1 has digital filters with such two-stage configurations to convert the sampling frequency. That is, the digital signal 8 output from the A/D converter 7 is first converted into the digital signal 10 of an intermediate sampling frequency b.multidot.fs by passing through the first decimation filter 9 which is the first digital filter (M taps) at the sampling frequency a.multidot.fs to subsample the sample data. Thereafter, components such as noises still in the vicinity of the signal band are further removed by the second decimation filter 11 which is the second digital filter (N taps) of a higher accuracy, to subsample the data to the final sampling frequency fs.
Filter characteristics of the above-mentioned first decimation filter 9 and second decimation filter 11, which are the first and second digital filters, are decided respectively by the coefficient generating devices 17 and 18.
Next, the operation of D/A conversion unit 2 is described.
D/A conversion unit 2 basically operates in the opposite way of A/D conversion unit 1. Though the conversion takes place in A/D conversion unit 1 by thinning the sampling frequency from a.multidot.fs to fs, in D/A conversion unit 2, the sampling frequency is, conversely, interpolated from fs to d.multidot.fs for conversion. Moreover, when the sampling frequency is converted into d.multidot.fs from fs in D/A conversion unit 2, it is passed through the digital filter to remove out-of-band signal noises as is the case with A/D conversion unit 1.
The digital filter used for such purpose should satisfy the following two conditions (c) and (d).
(c) In order to remove the image noises generated by interpolation, a sufficient attenuation is necessary in the filter characteristics in the region where there are image noises.
(d) It should have signal passing characteristics which are as flat as possible in a signal band.
Hereupon, from the fact that the conditions (c) and (d) are substantially quite similar to the conditions (a) and (b) associated with the filter for the subsampling process mentioned above, a two-stage configuration having the entirely same characteristics as the decimating filter is generally adopted in the interpolating filter.
That is, the digital signal of sampling frequency fs input from the digital signal input terminal 5 is first interpolated by the first interpolation filter 16, which is the third digital filter (N taps), and converted into a digital signal 15 of sampling frequency c.multidot.fs. Next, the digital signal 15 is interpolated by the second interpolation filter 14 which is the fourth digital filter (M taps) and converted into the sampling frequency d.multidot.fs, thereafter, the image noises are removed and it turns into a digital signal 13. The digital signal 13 with a sampling frequency of d.multidot.fs is converted into the analog signal by the oversampling type D/A converter 12, and output from the analog signal output terminal 6 of the D/A conversion unit 2.
FIG. 2 is a block diagram showing a general configuration which is common to the first decimation filter 9, second decimation filter 11, first interpolation filter 16 and second interpolation filter 14 which are the first, second, third and fourth digital filters.
In FIG. 2, numeral 40 designates a memory, into which digital input signals to respective filters are input and data for each tap of the filters are stored. Numeral 41 designates a memory, which stores filter characteristics of the filters and corresponds to the coefficient generating devices 17, 18, 19 and 20 in FIG. 1. Data stored in the memories 40 and 41 are given to a multiplier 42, whose calculation results are given to an accumulator 43.
By such a configuration, the sum of product operations or filter operations are performed in the digital filters.
The data capacity of memory 40 into which the digital signal is input differs with respective filters, that is, it is M words in the first decimation filter 9, which is the first digital filter, N words in the second decimation filter 11, which is the second digital filter, N/c words in the first interpolation filter 16, which is the third digital filter and Mc/d words in the second interpolation filter 14, which is the fourth digital filter.
The conventional oversampling type A/D-D/A converting apparatus as stated above is particularly disclosed in "A-D/D-A Conversion Techniques of Oversampling Type" (Nikkei Electronics, No. 458, pp. 223-231, Oct. 17, 1988).
Now, since the conventional A/D-D/A converting apparatus employs the configuration as stated above, the 4-stage digital filters from the first to fourth stages are needed, and the coefficient generating devices and the multipliers for multiplying the coefficient and digital data are necessary for the respective digital filters. Thus, there is a problem that the circuit required to implement the entire apparatus is considerably large.
In view of such circumstances, the inventor has proposed the invention which was previously disclosed in Japanese Patent Application Laid-Open No. 3-41826 (1991).
An embodiment of the invention disclosed in the Japanese Patent Application Laid-Open No. 3-41826 (1991) is shown in block diagram as FIG. 3. Similar reference characters in FIG. 1 and FIG. 3 designate similar component members therein.
The embodiment of Japanese Patent Application Laid-Open No. 3-41826 (1991) shown in FIG. 3 has been devised in view of the fact that, frankly speaking, the filter characteristics of the first decimation filter 9 in the A/D converting unit 1 shown in FIG. 1, which is the first digital filter, and the second interpolation filter 14 in D/A conversion unit 2, which is the fourth digital filter, are common, and the filter characteristics of the second decimation filter 11 in A/D conversion unit 1, which is the second digital filter and the first interpolation filter 16 in D/A conversion unit 2, which is the third digital filter, are common. That is, the coefficient generating devices 17 and 19 in FIG. 1 are replaced with a coefficient generating device 37 in FIG. 3, and the coefficient generating devices 18 and 20 are replaced with a coefficient generating device 38 in FIG. 3.
However, even in the aforesaid invention of Japanese Patent Application Laid-Open No. 3-41826 (1991), the coefficient generating devices are only reduced to four from two, thus it is not too much to say that little contribution is made for reducing the circuit configuration.